A CAM has been known as a memory to be used in a router for relaying a packet between different network addresses and selecting a direction in an internet communication network. As an example of the CAM, there has been known a memory of a ternary type which serves to store the 2-bit information of a data comparison mask in a memory cell and to output the result of a comparison with input data to a comparison match line (for example, see Patent Document 1).
In an LSI for a CAM which compares data having a large capacity, hundreds to thousands of CAM macro cells of approximately 64 entries by 72 bits are provided, for example, and a search table of several k entries is constituted wholly. The CAM macro cell uses, as a mainstream, a method of precharging a match signal line and activating a comparison data line when comparing data for a comparison with the internal data of a memory cell, and discharging the electric charge of the match signal line even if one bit is mismatched. As a whole, a very small number of data are matched and most of data are mismatched. For this reason, in the case in which data in all entries on a chip are compared with each other, the charge/discharge of the electric charges of the comparison data line and the match signal line is repeated every cycle because most of the data are mismatched. As a countermeasure, for example, there has been proposed a method of dividing comparison data into a plurality of portions and comparing them (for example, Patent Document 2). According to this method, a second comparing match signal line is precharged only when the divided data are matched with each other and the precharging is not carried out when they are mismatched based on the result of a first comparison for the divided data. Thus, the number of the charging/discharging operations of the match signal line is decreased and an operating current is reduced.
Moreover, there has been known a technique for cascade connecting a plurality of CAM chips to increase the number of entries when using the respective CAM chips as a system (for example, Patent Documents 3 to 5 and Non-Patent Document 1).
Patent Document 1: U.S. Pat. No. 6,154,384 Specification
Patent Document 2: U.S. Pat. No. 6,242,280 Specification
Patent Document 3: U.S. Pat. No. 5,930,359 Specification
Patent Document 4: US Patent Application Laid-Open No. 2004/0001380 Specification
Patent Document 5 US Patent Application Laid-Open No. 2004/0042241A1 Specification
Non-Patent Document 1 ISSCC 2004/Session 11/DRAM/11.5, “A 143 MHz 1.1W4.5 Mb Dynamic TCAM with Hierarchical Searching and Shift Redundancy Architecture”, 2004 IEEE ISSCC pp. 208-209, 522-523